1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a semiconductor structure having devices on both sides of the structure.
2) Description of the Prior Art
Mobility degradation is a major concern for transistor scaling due to higher channel doping, higher vertical field, and the use of high-k gate dielectric materials. In addition, due to the different substrate requirements for carrier mobility enhancement in NMOS and PMOS devices, the current technology for forming CMOS devices on the same substrate/platform will face severe limitations in the future. For e.g., it is known that Ge hole mobility is much higher than Si hole mobility.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following.
Chow, et al., Process Compatible Polysilicon-Based Electrical Through-Wafer Interconnects in Silicon Substrates, JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 11, NO. 6, DECEMBER 2002 631. thru wafer interconnects.
US 2004/0106268 Shaheen et al. shows a wafer bonding process.
US 2002/0195602—Klosowiak shows a process for a substrate.
US 20040072409 Fitzgerald, et al. Apr. 15, 2004—Coplanar integration of lattice-mismatched semiconductor with silicon via wafer bonding virtual substrates.
U.S. Pat. No. 6,774,447B2 Han—shows a process for stacking multiple substrates.
U.S. Pat. No. 6,194,290B2 Kub et al.—shows a direct bonding technique.
Laura Peters, Wafer Bonding Enables New Technologies and Applications, Nov. 1, 2003, Semiconductor International, http://www.reed-electronics.com/semiconductor/index.asp?layout=articlePrint&articleID=CA331034.—discusses various wafer bonding techniques and applications.